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preliminary rev. 0.4 11/10 copyright ? 2010 by silicon laboratories si5325 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si5325 p-p rogrammable p recision c lock m ultiplier description the si5325 is a low jitter, precision clock multiplier for applications requiring clock mu ltiplication without jitter attenuation. the si5325 accepts dual clock inputs ranging from 10 to 710 mhz and generates two clock outputs ranging from 10 to 945 mhz and select frequencies to 1.4 ghz. the two outputs are divided down separately from a common source. the device provides frequency translation combinations across this operating range. the si5325 input clock frequency and clock multiplication ratio are programmable through an i 2 c or spi interface. the si5325 is based on silicon laboratories' 3rd-generation dspll ? technology, which provides frequency synthesis in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the dspll loop bandwidth is digitally programmable. operating from a single 1.8, 2.5, or 3.3 v supply, t he si5325 is ideal for providing clock multiplication in high performance timing applications . applications ? sonet/sdh oc-48/stm-16 and oc-192/stm-64 line cards ? gbe/10gbe, 1/2/4/ 8/10gfc line cards ? itu g.709 and custom fec line cards ? optical modules ? wireless basestations ? data converter clocking ? xdsl ? sonet/sdh + pdh clock synthesis ? test and measurement features ? generates frequencies from 10 to 945 mhz and select frequencies to 1.4 ghz from an input frequency of 10 to 710 mhz ? low jitter clock outputs with jitter generation as low as 0.5 ps rms (12 khz?20 mhz) ? integrated loop filter with selectable loop bandwidth (150 khz to 2 mhz) ? dual clock inputs w/manual or automatically controlled switching ? dual clock outputs with selectable signal format (lvpecl, lvds, cml, cmos) ? support for itu g.709 and custom fec ratios (255/238, 255/237, 255/236) ? los, fos alarm outputs ? digitally-controlled ou tput phase adjust ? i 2 c or spi programmable ? on-chip voltage regulator for 1.8 5%, 2.5 or 3.3 v 10% operation ? small size: 6 x 6 mm 36-lead qfn ? pb-free, rohs compliant p reliminary d ata s heet dspll ? ckout2 ckin1 ckout1 ckin2 n31 n2 nc1_ls signal detect device interrupt vdd (1.8, 2.5, or 3.3 v) gnd n32 clock select i 2 c/spi port control alarms n1_hs nc2_ls
si5325 2 preliminary rev. 0.4
si5325 preliminary rev. 0.4 3 t able of c ontents section page 1. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.1. further documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2. pin descriptions: si5325 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 5. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6. package outline: 36-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7. recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8. top mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
si5325 4 preliminary rev. 0.4 table 1. performance specifications (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit temperature range t a ?40 25 85 oc supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 v 1.71 1.8 1.89 v supply current i dd f out = 622.08 mhz both ckouts enabled lvpecl format output ?251279ma ckout2 disabled ? 217 243 ma f out = 19.44 mhz both ckouts enabled cmos format output ?204234ma ckout2 disabled ? 194 220 ma disable mode ? 165 ? ma input clock frequency (ckin1, ckin2) ck f input frequency and clock multi- plication ratio determined by programming device pll divid- ers. consult silicon laboratories configuration software dspll- sim at www.silabs.com/timing (click on documentation) to determine pll divider settings for a given input frequency/clock multiplication ratio combination. 10 ? 710 mhz output clock frequency (ckout1, ckout2) ck of .002 970 1213 ? ? ? 945 1134 1400 mhz input clocks (ckin1, ckin2) input voltage level limits ckn vin 0?v dd v differential voltage swing ckn dpp 0.25 ? ? v pp common mode voltage ckn vcm 1.8 v 5% 0.9 ? 1.4 v 2.5 v 10% 1.0 ? 1.7 v 3.3 v 10% 1.1 ? 1.95 v rise/fall time ckn trf 20?80% ? 11 ns duty cycle (minimum pulse width) ckn dc whichever is smaller 40 ? 60 % 2??ns output clocks (ckout1, ckout2) common mode v ocm lvpecl 100 ? load line-to-line v dd ?1.42 ? v dd ?1.25 v differential output swing v od 1.1 ? 1.9 v single ended output swing v se 0.5 ? 0.93 v rise/fall time cko trf 20?80% ? 230 350 ps duty cycle uncertainty cko dc lvpecl differential 100 ? line-to-line measured at 50% point ?40 ? 40 ps note: for a more comprehensive listing of device specificat ions, please consult the silicon laboratories any-frequency precision clock family reference manual. this document can be downloaded from www.silabs.com/timing (click on documentation) .
si5325 preliminary rev. 0.4 5 pll performance jitter generation j gen f in = f out = 622.08 mhz, lvpecl output format 50 khz?80 mhz ?0.47?ps rms 12 khz?20 mhz ? 0.48 ? ps rms jitter transfer j pk ?0.050.1db phase noise cko pn f in = f out = 622.08 mhz 100 hz offset ??85?dbc/hz 1 khz offset ? ?90 ? dbc/hz 10 khz offset ? ?113 ? dbc/hz 100 khz offset ? ?118 ? dbc/hz 1 mhz offset ? ?132 ? dbc/hz subharmonic noise sp subh phase noise @ 100 khz offset ??88?dbc spurious noise sp spur max spur @ n x f3 (n > 1, n x f3 < 100 mhz) ??93?dbc package thermal resistance junction to ambient ? ja still air ? 38 ? oc/w table 2. absolute maximum ratings parameter symbol value unit dc supply voltage v dd ?0.5 to 3.8 v lvcmos input voltage v dig ?0.3 to (v dd + 0.3) v ckinn voltage level limits ckn vin 0 to v dd v operating junction temperature t jct ?55 to 150 c storage temperature range t stg ?55 to 150 c esd hbm tolerance (100 pf, 1.5 k ? ); all pins except ckin+/ckin? 2kv esd mm tolerance; all pins except ckin+/ckin? 150 v esd hbm tolerance (100 pf, 1.5 k ? ); ckin+/ckin? 750 v esd mm tolerance; ckin+/ckin? 100 v latch-up tolerance jesd78 compliant note: permanent device damage may occur if the absolute maximu m ratings are exceeded. functional operation should be restricted to the conditions as specified in the operation se ctions of this data sheet. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. table 1. performance specifications (continued) (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit note: for a more comprehensive listing of device specificat ions, please consult the silicon laboratories any-frequency precision clock family reference manual. this document can be downloaded from www.silabs.com/timing (click on documentation) .
si5325 6 preliminary rev. 0.4 figure 1. typical phase noise plot jitter bandwidth rms jitter (fs) oc-48, 12 khz to 20 mhz 374 oc-192, 20 khz to 80 mhz 388 oc-192, 4 mhz to 80 mhz 181 oc-192, 50 khz to 80 mhz 377 broadband, 800 hz to 80 mhz 420 622 mhz in, 622 mhz out bw=877 khz -170 -150 -130 -110 -90 -70 -50 1000 10000 100000 10000 00 10000000 100000000 offset frequency (hz) phase noise (dbc/ h
si5325 preliminary rev. 0.4 7 figure 2. si5325 typical application circuit (i 2 c control mode) figure 3. si5325 typical application circuit (spi control mode) si5325 int_c1b c2b rst ckout1+ ckout1? vdd gnd serial data serial clock reset interrupt/ckin_1 invalid indicator ckin_2 invalid indicator clock outputs ckout2+ ckout2? sda scl i 2 c interface serial port address a[2:0] cmode control mode (l) ckin1+ ckin1? input clock sources* ckin2+ ckin2? assumes differential lvpecl termination (3.3 v) on clock inputs. *note: ferrite bead system power supply c 3 c 2 c 1 c 4 0.1 f 0.1 f 0.1 f 1 f 0.1 f 100 ? 0.1 f + ? 0.1 f 100 ? 0.1 f + ? 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v si5325 int_c1b c2b spi interface rst ckout1+ ckout1? vdd gnd reset interrupt/clkin_1 invalid indicator clkin_2 invalid indicator ckout2+ ckout2? serial data out serial data in sdo sdi serial clock sclk slave select ss cmode control mode (h) ckin1+ ckin1? input clock sources* ckin2+ ckin2? assumes differential lvpecl termination (3.3 v) on clock inputs. *note: clock outputs 0.1 f 100 ? 0.1 f + ? 0.1 f 100 ? 0.1 f + ? ferrite bead system power supply c 3 c 2 c 1 c 4 0.1 f 0.1 f 0.1 f 1 f 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v
si5325 8 preliminary rev. 0.4 1. functional description the si5325 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. the si5325 accepts dual clock inputs ranging from 10 to 710 mhz and generates two synchronous clock outputs ranging from 10 to 945 mhz and select frequencies to 1.4 ghz. the device provides frequency translation across this operating range. independent dividers are available for each input clock and output clock, so the si 5325 can accept input clocks at different frequencies and it can generate output clocks at different frequencies. the si5325 input clock frequency and clock multiplication ratio are programmable through an i 2 c or spi interface. silicon laboratories offers a pc-based software utility, dspll sim , that can be used to determine the optimum pll divider settings for a given input frequency/clock multiplication ratio combinat ion that minimizes phase noise and power consumpt ion. this utility can be downloaded from http://www.silabs.com/timing (click on documentation). the si5325 is based on s ilicon laboratories' 3rd- generation dspll ? technology, which provides frequency synthesis in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the si5325 pll loop bandwidth is digitally programmable and supports a range from 30 khz to 1.3 mhz. the dspll sim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. in the case when the input clocks enter alarm conditions, the pll will freeze the dco output frequency near its last val ue to maintain operation with an internal state close to the last valid operating state. the si5325 has two differential clock outputs. the electrical format of each clock output is independently programmable to support lvpecl, lvds, cml, or cmos loads. if not required, the second clock output can be powered down to minimize power consumption. in addition, the phase of one output clock may be adjusted in relation to th e phase of the other output clock. the resolution varies from 800 ps to 2.2 ns depending on the pll divider settings. consult the dspll sim configuration software to determine the phase offset resolution for a given input clock/clock multiplication ratio combin ation. for system-level debugging, a bypass mode is available which drives the output clock directly from th e input clock, bypassing the internal dspll. the device is powered by a single 1.8, 2.5, or 3.3 v supply. 1.1. further documentation consult the silicon labo ratories any-frequency precision clock family re ference manual (frm) for detailed information about the si5325. additional design support is available from silicon laborat ories through your distributor. silicon laboratories has developed a pc-based software utility called dspll sim to simplify device configuration, including frequency planning and loop bandwidth selection. the frm and this utility can be downloaded from http://www.silabs.com/timing ; click on documentation.
si5325 preliminary rev. 0.4 9 2. pin descriptions: si5325 pin numbers are preliminary and subject to change. table 3. si5325 pin descriptions pin # pin name i/o signal level description 1rst ilvcmos external reset. active low input that performs external hardware reset of device. resets all internal logi c to a known state and forces the device registers to their def ault value. clock outputs are tristated during reset. the part must be programmed after a reset or power-on to get a clock output. see family refer- ence manual for details. this pin has a weak pull-up. 2, 7, 9, 14, 18, 30, 33 nc no connect. this pin must be left unc onnected for normal operation. 3 int_c1b o lvcmos interrupt/ckin1 invalid indicator. this pin functions as a device interrupt output or an alarm output for ckin1. if used as an interrupt output, int_pin must be set to 1. the pin functions as a maskable interrupt output with active polarity controlled by the int_pol register bit. if used as an alarm output, t he pin functions as a los (and optionally fos) alarm indicator for ckin1. set ck1_bad_pin = 1 and int_pin =0. 0 = ckin1 present. 1 = los (fos) on ckin1. the active polarity is controlled by ck_bad_pol . if no func- tion is selected, the pin tristates. note: internal register names are indicated by underlined italics, e.g., int_pin . see si5325 register map. 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 nc nc rst c2b int_c1b gnd vdd gnd vdd vdd clkin2+ clkin2? nc vdd clkin1+ clkin1? cs_ca scl sda_sdo a1 a2_ss sdi clkout1? nc gnd vdd nc clkout2? clkout2+ cmode gnd pad a0 gnd 9 18 19 28 nc nc gnd clkout1+
si5325 10 preliminary rev. 0.4 4c2bolvcmos ckin2 invalid indicator. this pin functions as a los (and optionally fos) alarm indi- cator for ckin2 if ck2_bad_pin =1. 0 = ckin2 present. 1 = los (fos) on ckin2. the active polarity can be changed by ck_bad_pol . if ck2_bad_pin = 0, the pin tristates. 5, 10, 11, 15, 32 v dd v dd supply supply. the device operates from a 1.8, 2.5, or 3.3 v supply. bypass capacitors should be associated with the following vdd pins: 5 0.1 f 10 0.1 f 32 0.1 f a 1.0 f should also be placed as close to device as is prac- tical. 6, 8, 19, 20 31 gnd gnd supply ground. must be connected to system ground. minimize the ground path impedance for optimal performance of this device. 12 13 ckin2+ ckin2? imulti clock input 2. differential input clock. this input can also be driven with a single-ended signal. input frequency range is 10 to 710 mhz. 16 17 ckin1+ ckin1? imulti clock input 1. differential input clock. this input can also be driven with a single-ended signal. input frequency range is 10 to 710 mhz. 21 cs_ca i/o lvcmos input clock select/active clock indicator. input : in manual clock selection mode, this pin functions as the manual input clock selector if the cksel_pin is set to 1. 0 = select ckin1. 1 = select ckin2. if cksel_pin =0, the cksel_reg register bit controls this function. if configured as input, must be set high or low. output : in automatic clock selection mode, this pin indicates which of the two input clocks is currently the active clock. if alarms exist on both clocks, ca will indicate the last active clock that was used before entering the vco freeze state. the ck_actv_pin register bit must be set to 1 to reflect the active clock status to the ca output pin. 0 = ckin1 active input clock. 1 = ckin2 active input clock. if ck_actv_pin = 0, this pin will tristate. the ca status will always be reflected in the ck_actv_reg read only register bit. table 3. si5325 pin descriptions (continued) pin # pin name i/o signal level description note: internal register names are indicated by underlined italics, e.g., int_pin . see si5325 register map.
si5325 preliminary rev. 0.4 11 22 scl i lvcmos serial clock/ serial clock. this pin functions as the serial clock input for both spi and i 2 c modes. this pin has a weak pulldown. 23 sda_sdo i/o lvcmos serial data. in i 2 c control mode (cmode = 0), this pin functions as the bidirectional serial data port. in spi control mode (cmode = 1), this pin functions as the serial data output. 25 24 a1 a0 ilvcmos serial port address. in i 2 c control mode (cmode = 0), these pins function as hardware controlled address bits. the i 2 c address is 1101 [a2] [a1] [a0]. in spi control mode (cmode = 1), these pins are ignored. this pin has a weak pulldown. 26 a2_ss ilvcmos serial port address/slave select. in i 2 c control mode (cmode = 0), this pin functions as a hardware controlled address bit [a2]. in spi control mode (cmode = 1), this pin functions as the slave select input. this pin has a weak pulldown. 27 sdi i lvcmos serial data in. in i 2 c control mode (cmode = 0), this pin is ignored. in spi control mode (cmode = 1), this pin functions as the serial data input. this pin has a weak pulldown. 29 28 ckout1? ckout1+ omulti output clock 1. differential output clock with a frequency range of 10 mhz to 1.4175 ghz. output signal format is selected by sfout1_reg register bits. output is differential for lvpecl, lvds, and cml compatible modes. for cmos for- mat, both output pins drive identical single-ended clock out- puts. 34 35 ckout2? ckout2+ omulti output clock 2. differential output clock with a frequency range of 10 mhz to 1.4175 ghz. output signal format is selected by sfout2_reg register bits. output is differential for lvpecl, lvds, and cml compatible modes. for cmos for- mat, both output pins drive identical single-ended clock out- puts. 36 cmode i lvcmos control mode. selects i 2 c or spi control mode for the si5325. 0 = i 2 c control mode. 1 = spi control mode. must not float. gnd pad gnd gnd supply ground pad. the ground pad must provide a low thermal and electrical impedance to a ground plane. table 3. si5325 pin descriptions (continued) pin # pin name i/o signal level description note: internal register names are indicated by underlined italics, e.g., int_pin . see si5325 register map.
si5325 12 preliminary rev. 0.4 3. register map all register bits that are not defined in this map shou ld always be written with the specified reset values. the writing to these bits of values other than the specif ied reset values may result in undefined device behavior. registers not listed, such as register 64, should never be written to. register d7 d6 d5 d4 d3 d2 d1 d0 0ckout_ always_ on bypass_ reg 1 ck_prior2[1:0] ck_prior[1:0] 2 bwsel_reg[3:0] 3 cksel_reg[1:0] sq_ical 4 autosel_reg[1:0] 5 icmos[1:0] 6 sleep sfout2_reg[2:0} sfout1_reg[2:0] 7 fosrefsel[2:0] 8 hlog_2[1:0] hlog_1[1:0] 10 dsbl2_ reg dsbl1_ reg 11 pd_ck2 pd_ck1 19 fos_en fos_thr[1:0] valtime[1:0] 20 ck2_ bad_ pin ck1_ bad_ pin int_pin 21 ck1_actv_ pin cksel_pin 22 ck_actv_ pol ck_bad_ pol int_pol 23 los2_msk los1_msk 24 fos2_msk fos1_msk 25 n1_hs[2:0] 31 nc1_ls[19:16] 32 nc1_ls[15:8] 33 nc1_ls[7:0] 34 nc2_ls[19:16] 35 nc2_ls[15:8] 36 nc2_ls[7:0]
si5325 preliminary rev. 0.4 13 40 n2_ls[19:16] 41 n2_ls[15:8] 42 n2_ls[7:0] 43 n31[18:16] 44 n31[15:8] 45 n31[7:0] 46 n32[18:16] 47 n32[15:8] 48 n32[7:0] 55 clkin2rate[2:0] clkin1rate[2:0] 128 ck2_actv_ reg ck1_actv_ reg 129 los2_int los1_int 130 clat- progress dighold- valid fos2_int fos1_int 131 los2_flg los1_flg 132 fos2_flg fos1_flg 134 partnum_ro[11:4] 135 partnum_ro[3:0] revid_ro[3:0] 136 rst_reg ical grade_ro[1:0] 138 los2_en [1:1] los1_en [1:1] 139 los2_en [0:0] los1_en [0:0] fos2_en fos1_en 142 independentskew1[7:0] 143 independentskew2[7:0] 185 nvm_revid[7:0] register d7 d6 d5 d4 d3 d2 d1 d0
si5325 14 preliminary rev. 0.4 4. register descriptions reset value = 0001 0100 register 0. bitd7d6d5d4d3d2d1d0 name reserved reserved ckout_ always_ on reserved reserved reserved bypass_ reg reserved type rrr/wrrrr/wr bit name function 7:6 reserved reserved. 5ckout_ always_on ckout always on. this will bypass the sq_ical func tion. output will be availabl e even if sq_ical is on and ical is not complete or successful. see table 4 on page 46. 0: squelch output until pa rt is calibrated (ical). 1: provide an output. note: the frequency may be significantly off until the part is cali- brated. 4:2 reserved reserved. 1 bypass_ reg bypass register. this bit enables or disables the pll bypass mode. use only when the device is in vco freeze or before the first ical. bypass mode is not supported for cmos output clocks. 0: normal operation 1: bypass mode. selected input clock is c onnected to ckout buffers, bypassing pll. 0 reserved reserved.
si5325 preliminary rev. 0.4 15 reset value = 1110 0100 reset value = 0100 0010 register 1. bitd7d6d5d4d3d2d1d0 name reserved ck_prior2 [1:0] ck_prior1 [1:0] type rr/wr/w bit name function 7:4 reserved reserved. 3:2 ck_prior2 [1:0] ck_prior 2. selects which of the input clocks will be 2nd priority in the autose lection state machine. 00: ckin1 is 2nd priority. 01: ckin2 is 2nd priority. 10: reserved 11: reserved 1:0 ck_prior1 [1:0] ck_prior 1. selects which of the input clocks will be 1st priority in the autose lection state machine. 00: ckin1 is 1st priority. 01: ckin2 is 1st priority. 10: reserved 11: reserved register 2. bitd7d6d5d4d3d2d1d0 name bwsel_reg [3:0] reserved type r/w r bit name function 7:4 bwsel_reg [3:0] bwsel_reg. selects nominal f3db bandwidth for pll. see the dspllsim for settings. after bwsel_reg is written with a new value, an ical is required for the change to take effect. 3:0 reserved reserved.
si5325 16 preliminary rev. 0.4 reset value = 0000 0101 register 3. bitd7d6d5d4d3d2d1d0 name cksel_reg [1:0] reser ved sq_ical reserved type r/w r r/w r bit name function 7:6 cksel_reg [1:0] cksel_reg. if the device is operating in regi ster-based manual clock selection mode (autosel_reg = 00), and cksel_pin = 0, then these bits select which input clock will be the active input clock. if ckse l_pin = 1 and autosel_reg = 00, the cs_ca input pin continues to co ntrol clock selection and cksel_reg is of no consequence . 00: ckin_1 selected. 01: ckin_2 selected. 10: reserved 11: reserved 5 reserved reserved. 4 sq_ical sq_ical. this bit determines if the output clocks will remain enabled or be squelched (disabled) during an internal calibration. see table 4 on page 46. 0: output clocks enabled during ical. 1: output clocks disabled during ical. 3:0 reserved reserved.
si5325 preliminary rev. 0.4 17 reset value = 0001 0010 reset value = 1110 1101 register 4. bitd7d6d5d4d3d2d1d0 name autosel_reg [1:0] reserved reserved type r/w r r bit name function 7:6 autosel_ reg [1:0] autosel_reg [1:0] . selects method of input clock selection to be used. 00: manual (either register or pin controlled, see cksel_pin) 01: automatic non-revertive 10: automatic revertive 11: reserved 5:0 reserved reserved. register 5. bitd7d6d5d4d3d2d1d0 name icmos [1:0] reserved type r/w r bit name function 7:6 icmos [1:0] icmos [1:0]. when the output buffer is set to cmos mode, these bits determine the output buffer drive strength. the first number below refers to 3.3 v operation; the second to 1.8 v operation. these values assume ckout+ is tied to ckout-. 00: 8ma/2ma. 01: 16ma/4ma 10: 24ma/6ma 11: 32ma/8ma 5:0 reserved reserved.
si5325 18 preliminary rev. 0.4 reset value = 0010 1101 register 6. bitd7d6d5d4d3d2d1d0 name reserved sleep sfout2_reg [2:0] sfout1_reg [2:0] type rr/w r/w r/w bit name function 7 reserved reserved. 6sleep sleep. in sleep mode, all clock outputs are disabled and the maximum amount of internal cir- cuitry is powered down to reduce power dissipation and noise generation. this bit over- rides the sfoutn_reg[2:0] ou tput signal format settings. 0: normal operation 1: sleep mode 5:3 sfout2_ reg [2:0] sfout2_reg [2:0]. controls output signal format and disable for ckout2 output buffer. bypass mode is not supported for cmos output clocks. 000: reserved 001: disable 010: cmos 011: low swing lvds 100: reserved 101: lvpecl 110: cml 111: lvds 2:0 sfout1_ reg [2:0] sfout1_reg [2:0]. controls output signal format and disable for ckout1 output buffer. bypass mode is not supported for cmos output clocks. 000: reserved 001: disable 010: cmos 011: low swing lvds 100: reserved 101: lvpecl 110: cml 111: lvds
si5325 preliminary rev. 0.4 19 reset value = 0010 1010 register 7. bitd7d6d5d4d3d2d1d0 name reserved fosr efsel [2:0] type rr/w bit name function 7:3 reserved. reserved. 2:0 fosrefsel [2:0] fosrefsel [2:0]. selects which input clock is used as the reference frequency fo r frequency off-set (fos) alarms. 000: xa/xb (external reference) 001: ckin1 010: ckin2 011: reserved 100: reserved 101: reserved 110: reserved 111: reserved
si5325 20 preliminary rev. 0.4 reset value = 0000 0000 register 8. bitd7d6d5d4d3d2d1d0 name hlog_2[1:0] hlog_1[1:0] reserved type r/w r/w r bit name function 7:6 hlog_2 [1:0] hlog_2 [1:0]. 00: normal operation 01: holds ckout2 output at st atic logic 0. entrance and ex it from this state will occur without glitches or runt pulses. 10:holds ckout2 output at static logic 1. entrance and exit from this state will occur without glitches or runt pulses. 11: reserved 5:4 hlog_1 [1:0]. 00: normal operation 01: holds ckout1 output at st atic logic 0. entrance and ex it from this state will occur without glitches or runt pulses. 10: holds ckout1 output at st atic logic 1. entrance and ex it from this state will occur without glitches or runt pulses. 11: reserved 3:0 reserved reserved.
si5325 preliminary rev. 0.4 21 reset value = 0000 0000 reset value = 0100 0000 register 10. bitd7d6d5d4d3d2d1d0 name reserved dsbl2_ reg dsbl1_ reg reserved reserved type rr/wr/wrr bit name function 7:4 reserved reserved. 3 dsbl2_reg dsbl2_reg. this bit controls the powerdown of the ck out2 output buffer. if disable mode is selected, the nc2 output divider is also powered down. 0: ckout2 enabled 1: ckout2 disabled 2 dsbl1_reg dsbl1_reg. this bit controls the powerdown of the ck out1 output buffer. if disable mode is selected, the nc1 output divider is also powered down. 0: ckout1 enabled 1: ckout1 disabled 1:0 reserved reserved. register 11. bitd7d6d5d4d3d2d1d0 name reserved pd_ck2 pd_ck1 type rr/wr/w bit name function 7:2 reserved reserved. 1pd_ck2 pd_ck2. this bit controls the powerdown of the ckin2 input buffer. 0: ckin2 enabled 1: ckin2 disabled 0pd_ck1 pd_ck1. this bit controls the powerdown of the ckin1 input buffer. 0: ckin1 enabled 1: ckin1 disabled
si5325 22 preliminary rev. 0.4 reset value = 0010 1100 register 19. bitd7d6d5d4d3d2d1d0 name fos_en fos_thr [1:0] val time [1:0] reserved type r/w r/w r/w r bit name function 7:5 fos_en fos_en. frequency offset enable globally disables fos. see the individual fos enables (fosx_en, register 139). 0: fos disable 1: fos enabled by fosx_en 6:5 fos_thr [1:0] fos_thr [1:0]. frequency offset at which fos is declared: 00: 11 to 12 ppm (stratum 3/3e compliant, with a stratum 3/3e used for refclk 01: 48 to 49 ppm (smc) 10: 30 ppm (sonet minimum clock (smc), with a stratum 3/3e used for refclk. 11: 200 ppm 4:3 valtime [1:0] valtime [1:0]. sets amount of time for input clock to be valid before the associated alarm is removed. 00: 2 ms 01: 100 ms 10: 200 ms 11: 13 seconds 2:0 reserved reserved.
si5325 preliminary rev. 0.4 23 reset value = 0011 1110 register 20. bitd7d6d5d4d3d2d1d0 name reserved ck2_bad_ pin ck1_bad_ pin reserved int_pin type rr/wr/wrr/w bit name function 7:4 reserved reserved. 3 ck2_bad_ pin ck2_bad_pin. the ck2_bad status can be reflected on the c2b output pin. 0: c2b output pin tristated 1: c2b status reflected to output pin 2 ck1_bad_ pin ck1_bad_pin. the ck1_bad status can be reflected on the c1b output pin. 0: c1b output pin tristated 1: c1b status reflected to output pin 1 reserved reserved. 0int_pin int_pin. reflects the interrupt status on the int_c1b output pin. 0: interrupt status not disp layed on int_c1b output pin. if ck1_bad_pin = 0, int_c1b output pin is tristated. 1: interrupt status reflected to output pi n. instead, the int_c1b pin indicates when ckin1 is bad.
si5325 24 preliminary rev. 0.4 reset value = 1111 1111 register 21. bitd7 d6d5d4d3d2 d1 d0 name reserved reserved ck1_actv_pin cksel_ pin type r force 1 r r r r r/w r/w bit name function 7:2 reserved reserved. 1 ck1_actv_pin ck1_actv_pin. the ck1_actv_reg status bit can be reflected to the cs_ca output pin using the ck1_actv_pin enable function. ck1_actv_ pin is of consequence only when pin controlled clock selection is being used. 0: cs_ca output pin tristated. 1: clock active status reflected to output pin. 0 cksel_pin cksel_pin. if manual clock selection is being used, clock selection can be controlled via the cksel_reg[1:0] register bits or the cs_ca input pin. this bit is only active when autosel_reg = manual. 0: cs_ca pin is ignored. cksel_reg[1:0] register bits control clock selection. 1: cs_ca input pin controls clock selection.
si5325 preliminary rev. 0.4 25 reset value = 1101 1111 register 22. bitd7d6d5d4 d3 d2 d1 d0 name reserved ck_actv_pol ck_ba d_ pol reserved int_pol type r r/w r/w r r/w bit name function 7:4 reserved reserved. 3 ck_actv_ pol ck_actv_pol. sets the active polarity for the cs_ca signals when reflected on an output pin. 0: active low 1: active high 2 ck_bad_ pol ck_bad_pol. sets the active polarity for the int_c1b and c2b signals when reflected on output pins. 0: active low 1: active high 1 reserved reserved. 0int_pol int_pol. sets the active polarity for the interrupt st atus when reflected on the int_c1b output pin. 0: active low 1: active high
si5325 26 preliminary rev. 0.4 reset value = 0001 1111 register 23. bitd7d6d5d4d3 d2 d1 d0 name reserved los2_ msk los1_ msk reserved type rr/wr/wr bit name function 7:3 reserved reserved. 2los2_msk los2_msk. determines if a los on ckin2 (los2_flg) is used in the generation of an interrupt. writes to this register do not change the value held in the los2_flg register. 0: los2 alarm triggers active interr upt on int_c1b output (if int_pin=1). 1: los2_flg ignored in generating interrupt output. 1los1_msk los1_msk. determines if a los on ckin1 (los1_flg) is used in the generation of an interrupt. writes to this register do not change the value held in the los1_flg register. 0: los1 alarm triggers active interr upt on int_c1b output (if int_pin=1). 1: los1_flg ignored in generating interrupt output. 0 reserved reserved.
si5325 preliminary rev. 0.4 27 reset value = 0011 1111 register 24. bitd7d6d5d4d3 d2 d1 d0 name reserved fos2_msk fos1_msk reserved type rr/wr/wr bit name function 7:3 reserved reserved. 2 fos2_msk fos2_msk. determines if the fos2 _flg is used to in the generation of an interrupt. writes to this register do not change the value held in the fos2_flg register. 0: fos2 alarm triggers active interr upt on int_c1b output (if int_pin=1). 1: fos2_flg ignored in generating interrupt output. 1 fos1_msk fos1_msk. determines if the fos1_flg is used in the gen eration of an interrupt. writes to this reg- ister do not change the value held in the fos1_flg register. 0: fos1 alarm triggers active interr upt on int_c1b output (if int_pin=1). 1: fos1_flg ignored in generating interrupt output. 0 reserved reserved.
si5325 28 preliminary rev. 0.4 reset value = 0010 0000 reset value = 0000 0000 register 25. bitd7d6d5d4d3d2d1d0 name n1_hs [2:0] reserved type r/w r bit name function 7:5 n1_hs [2:0] n1_hs [2:0]. sets value for n1 high speed divider which dr ives ncn_ls (n = 1 to 2) low-speed divider. 000: n1= 4 note: changing the coarse skew vi a the inc pin is disabled for this value. 001: n1= 5 010: n1=6 011: n1= 7 100: n1= 8 101: n1= 9 110: n1= 10 111: n1= 11 4:0 reserved reserved. register 31. bitd7d6d5d4d3d2d1d0 name reserved nc1_ls [19:16] type rr/w bit name function 7:4 reserved reserved. 3:0 nc1_ls [19:16] nc1_ls [19:16]. sets value for nc1 low-speed divider, which drives ckout1 output. must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20]
si5325 preliminary rev. 0.4 29 reset value = 0000 0000 reset value = 0011 0001 register 32. bitd7d6d5d4d3d2d1d0 name nc1_ls [15:8] type r/w bit name function 7:0 nc1_ls [15:8] nc1_ls [15:8]. sets value for nc1 low-speed divider, which drives ckout1 output. must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20] register 33. bitd7d6d5d4d3d2d1d0 name nc1_ls [7:0] type r/w bit name function 7:0 nc1_ls [19:0] nc1_ls [7:0]. sets value for nc1 low-speed divider, which drives ckout1 output. must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20]
si5325 30 preliminary rev. 0.4 reset value = 0000 0000 reset value = 0000 0000 register 34. bitd7d6d5d4d3d2d1d0 name reserved nc2_ls [19:16] type rr/w bit name function 7:4 reserved reserved. 3:0 nc2_ls [19:16] nc2_ls [19:16]. sets value for nc2 low-speed divider, which drives ckout2 output. must be 0 or odd. 00000000000000000000=1 00000000000000000001=2 00000000000000000011=4 00000000000000000101=6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20] register 35. bitd7d6d5d4d3d2d1d0 name nc2_ls [15:8] type r/w bit name function 7:0 nc2_ls [15:8] nc2_ls [15:8] . sets value for nc2 low-speed divider, which drives ckout2 output. must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20]
si5325 preliminary rev. 0.4 31 reset value = 0011 0001 reset value = 1100 0000 register 36. bitd7d6d5d4d3d2d1d0 name nc2_ls [7:0] type r/w bit name function 7:0 nc2_ls [7:0] nc2_ls [7:0]. sets value for nc2 low-speed divider, which drives ckout2 output. must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20] register 40. bitd7d6d5d4d3d2d1d0 name reserved n2_ls [19:16] type rr/w bit name function 7:4 reserved reserved. 3:0 n2_ls [19:16] n2_ls [19:16]. sets the value for the n2 low-speed divider, which drives the phase detector. must be an even number ranging from 32 to 512 (inclusive). 00000000000000100000 = 32 00000000000000100010 = 34 00000000000000100100 = 36 ... 00000000001000000000 = 512 valid divider values = [32, 34, 36...512]
si5325 32 preliminary rev. 0.4 reset value = 0000 0000 reset value = 1111 1001 register 41. bitd7d6d5d4d3d2d1d0 name n2_ls [15:8] type r/w bit name function 7:0 n2_ls [15:8] n2_ls [15:8]. sets the value for the n2 low-speed divider, which drives the phase detector. must be an even number ranging from 32 to 512 (inclusive). 00000000000000100000 = 32 00000000000000100010 = 34 00000000000000100100 = 36 ... 00000000001000000000 = 512 valid divider values = [32, 34, 36...512] register 42. bitd7d6d5d4d3d2d1d0 name n2_ls [7:0] type r/w bit name function 7:0 n2_ls [7:0] n2_ls [7:0]. sets the value for the n2 low-speed divider, which drives the phase detector. must be an even number ranging from 32 to 512 (inclusive). 00000000000000100000 = 32 00000000000000100010 = 34 00000000000000100100 = 36 ... 00000000001000000000 = 512 valid divider values = [32, 34, 36...512]
si5325 preliminary rev. 0.4 33 reset value = 0000 0000 reset value = 0000 0000 register 43. bitd7d6d5d4d3d2d1d0 name reserved n31 [18:16] type rr/w bit name function 7:3 reserved reserved. 2:0 n31 [18:16] n31 [18:16]. sets value for input divider for ckin1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 valid divider values=[1, 2, 3, ..., 2^19] register 44. bitd7d6d5d4d3d2d1d0 name n31_[15:8] type r/w bit name function 7:0 n31_[15:8] n31_[15:8]. sets value for input divider for ckin1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 valid divider values=[1, 2, 3, ..., 2^19]
si5325 34 preliminary rev. 0.4 reset value = 0000 1001 reset value = 0000 0000 register 45. bitd7d6d5d4d3d2d1d0 name n31_[7:0] type r/w bit name function 7:0 n31_[7:0 n31_[7:0]. sets value for input divider for ckin1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 valid divider values=[1, 2, 3, ..., 2^19] register 46. bitd7d6d5d4d3d2d1d0 name reserved n32_[18:16] type rr/w bit name function 7:3 reserved reserved. 2:0 n32_[18:16] n32_[18:16]. sets value for input divider for ckin2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 valid divider values=[1, 2, 3, ..., 2^19]
si5325 preliminary rev. 0.4 35 reset value = 0000 0000 reset value = 0000 1001 register 47. bitd7d6d5d4d3d2d1d0 name n32_[15:8] type r/w bit name function 7:0 n32_[15:8] n32_[15:8]. sets value for input divider for ckin2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 valid divider values=[1, 2, 3, ..., 2^19] register 48. bitd7d6d5d4d3d2d1d0 name n32_[7:0] type r/w bit name function 7:0 n32_[7:0] n32_[7:0]. sets value for input divider for ckin2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 valid divider values=[1, 2, 3, ..., 2^19]
si5325 36 preliminary rev. 0.4 reset value = 0000 0000 register 55h. bitd7d6d5d4d3d2d1d0 name reserved clkin2rate_[ 2:0] clkin1rate[2:0] type rr/w r/w bit name function 7:6 reserved reserved. 5:3 clkin2rate[2:0] clkin2rate[2:0]. ckinn frequency selection for fos alarm monitoring. 000: 10 - 27 mhz 001: 25 - 54 mhz 002: 50 - 105 mhz 003: 95 - 215 mhz 004: 190 - 435 mhz 005: 375 - 710 mhz 006: reserved 007: reserved 2:0 clkin1rate [2:0] clkin1rate[2:0]. ckinn frequency selection for fos alarm monitoring. 000: 10 - 27 mhz 001: 25 - 54 mhz 002: 50 - 105 mhz 003: 95 - 215 mhz 004: 190 - 435 mhz 005: 375 - 710 mhz 006: reserved 007: reserved
si5325 preliminary rev. 0.4 37 reset value = 0010 0000 reset value = 0000 0110 register 128. bitd7d6d5d4d3d2 d1 d0 name reserved ck2_actv_reg ck1_actv_reg type rrr bit name function 7:2 reserved reserved. 1 ck2_actv_reg ck2_actv_reg. indicates if ckin2 is currently t he active clock for the pll input. 0: ckin2 is not the active input clock. eith er it is not selected or los2_int is 1. 1: ckin2 is the active input clock. 0 ck1_actv_reg ck1_actv_reg. indicates if ckin1 is currently t he active clock for the pll input. 0: ckin1 is not the active input clock. eith er it is not selected or los1_int is 1. 1: ckin1 is the active input clock. register 129. bitd7d6d5d4d3d2d1d0 name reserved los2_int los1_int reserved type rrrr bit name function 7:3 reserved reserved. 2 los2_int los2_int. indicates the los status on ckin2. 0: normal operation. 1: internal loss-of-signal alarm on ckin2 input. 1 los1_int los1_int. indicates the los status on ckin1. 0: normal operation. 1: internal loss-of-signal alarm on ckin1 input. 0 reserved reserved.
si5325 38 preliminary rev. 0.4 reset value = 0000 0001 register 130. bit d7 d6d5d4d3d2d1d0 name clatprogress reserved fo s2_int fos1_int reserved type rrrrr bit name function 7clat- progress clat progress. indicates if the last change in the clat register has been processed. 0: coarse skew adjustment not in progress. 1: coarse skew adjustment in progress. 6:3 reserved reserved. 2fos2_int ckin2 frequency offset status. 0: normal operation. 1: internal frequency offset alarm on ckin2 input. 1fos1_int ckin1 frequency offset status. 0: normal operation. 1: internal frequency offset alarm on ckin1 input. 0 reserved reserved.
si5325 preliminary rev. 0.4 39 reset value = 0001 1111 register 131. bitd7d6d5d4d3d2d1d0 name reserved los2_flg los1_flg reserved type rr/wr/wr bit name function 7:3 reserved reserved. 2los2_flg ckin2 loss-of-signal flag. 0: normal operation. 1: held version of los2_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by lo s2_msk bit. flag cleared by writing 0 to this bit. 1los1_flg ckin1 loss-of-signal flag. 0: normal operation 1: held version of los1_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by lo s1_msk bit. flag cleared by writing 0 to this bit. 0 reserved reserved.
si5325 40 preliminary rev. 0.4 reset value = 0000 0010 register 132. bitd7d6d5d4d3d2d1d0 name reserved fos2_flg fos1_flg reserved reserved type rr/wr/wrr bit name function 7:4, 0 reserved reserved. 3fos2_flg clkin_2 frequency offset flag. 0: normal operation. 1: held version of fos2_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by fo s2_msk bit. flag cleared by writing 0 to this bit. 2fos1_flg clkin_1 frequency offset flag. 0: normal operation 1: held version of fos1_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by fo s1_msk bit. flag cleared by writing 0 to this bit. 1 reserved reserved.
si5325 preliminary rev. 0.4 41 reset value = 0000 0001 reset value = 1010 0010 register 134. bitd7d6d5d4d3d2d1d0 name partnum_ro [11:4] type r bit name function 7:0 partnum_ ro [11:0] device id (1 of 2). 0000 0001 1001: si5325 register 135. bitd7d6d5d4d3d2d1d0 name partnum_ro [3:0 ] revid_ro [3:0] type rr bit name function 7:4 partnum_ ro [11:0] device id (2 of 2). 0000 0001 1001: si5325 3:0 revid_ro [3:0] indicates revision number of device. 0000: revision a 0001: revision b 0010: revision c others: reserved
si5325 42 preliminary rev. 0.4 reset value = 0000 0000 register 136. bitd7d6d5d4d3d2d1d0 name rst_reg ical reserved grade_ro [1:0] type r/w r/w r r bit name function 7 rst_reg internal reset (same as pin reset). note: the i2c (or spi) port may not be accessed until 10 ms after rst_reg is asserted. 0: normal operation. 1: reset of all internal logic. outputs disabled or tristated during reset. 6ical start an internal calibration sequence. for proper operation, the device must go through an internal calibration sequence. ical is a self-clearing bit. writing a one to this location initiates an ic al. the calibration is complete once the lol alarm goes low. a valid stable clock (within 100 ppm) must be present to begin ical. note: any divider, clkinn_rate or bwsel _reg changes require an ical to take effect. 0: normal operation. 1: writing a "1" initiates intern al self-calibration. upon comple tion of internal self-calibra- tion, lol will go low. 5:2 reserved reserved. 1:0 grade_ro [1:0] indicates maximum clock output frequency of this device. limits the range of the n1_hs divider. 00: n1_hs x ncn_ls > 4. maximum clock output frequency = 1.4175 ghz. 01: n1_hs x ncn_ls > 6. maximum clock output frequency = 808 mhz. 10: n1_hs x ncn_ls > 14. maximum clock output frequency = 346 mhz. 11: n1_hs x ncn_ls > 20. maximum clock output frequency = 243 mhz.
si5325 preliminary rev. 0.4 43 reset value = 0000 1111 register 138. bitd7d6d5d4d3d2 d1 d0 name reserved los2_en [1:4] los1_en [1:1] type rr/wr/w bit name function 7:2 reserved reserved. 1 los2_en [1:0] enable ckin2 los monitoring on the specified input (2 of 2). note: los2_en is split between two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive versio n of los. see the family reference man- ual for details. 0 los1_en [1:0] enable ckin1 los monitoring on the specified input (1 of 2). note: los1_en is split between two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive versio n of los. see the family reference man- ual for details.
si5325 44 preliminary rev. 0.4 reset value = 1111 1111 register 139. bit d7 d6 d5 d4 d3 d2 d1 d0 name reserved los2_en [0:0] los1_en [0:0] reserved fos2_en fos1_en type r r/w r/w r r/w r/w bit name function 7:6, 3:2 reserved reserved. 5 los2_en [1:0] enable ckin2 los monitoring on the specified input (2 of 2). note: los2_en is split between two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive versio n of los. see the family reference manual for details 4 los1_en [1:0] enable ckin1 los monitoring on the specified input (1 of 2). note: los1_en is split between two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive versio n of los. see the family reference manual for details. 1fos2_en enables fos on a per channel basis. 0: disable fos monitoring. 1: enable fos monitoring. 0fos1_en enables fos on a per channel basis. 0: disable fos monitoring. 1: enable fos monitoring.
si5325 preliminary rev. 0.4 45 reset value = 0000 0000 reset value = 0000 0000 reset value = 0001 0011 register 142. bitd7d6d5d4d3d2d1d0 name independentskew1 [7:0] type r/w bit name function 7:0 independentskew1 [7:0] independentskew1. 8 bit field that represents a twos comp lement of the phase offset in terms of clocks from the high speed output divider. default = 0. register 143. bitd7d6d5d4d3d2d1d0 name independentskew2 [7:0] type r/w bit name function 7:0 independ-entskew2 [7:0] independentskew2. 8 bit field that represents a twos co mplement of the phase offset in terms of clocks from the high speed output divider. default = 0. register 185. bitd7d6d5d4d3d2d1d0 name nvm_revid [7:0] type r bit name function 7:0 nvm_revid [7:0] nvm_revid.
si5325 46 preliminary rev. 0.4 table 5 lists all of the register locations that should be followed by an ical after their contents are changed. table 4. ckout_always_on and sqical truth table ckout_always_on sqical resu lts output to output skew preserved? 0 0 ckout off until after the first ical n 0 1 ckout off until after the first successful ical (i.e., when lol is low) y 1 0 ckout always on, including during an ical n 1 1 ckout always on, including during an ical y table 5. register locations requiring ical addr register 0 bypass_reg 0 ckout_always_on 1 ck_prior2 1 ck_prior1 2 bwsel_reg 4hist_del 5icmos 7 fosrefsel 9hist_avg 10 dsbl2_reg 10 dsbl1_reg 11 pd_ck2 11 pd_ck1 19 fos_en 19 fos_thr 19 valtime 19 lockt 21 incdec_pin 25 n1_hs 31 nc1_ls 34 nc2_ls 40 n2_hs 40 n2_ls 43 n31 46 n32 55 clkin2rate 55 clkin1rate
si5325 preliminary rev. 0.4 47 5. ordering guide ordering part number output clock frequency range package rohs6, pb-free temperature range si5325a-c-gm 10?945 mhz 970?1134 mhz 1.213?1.417 ghz 36-lead 6 x 6 mm qfn yes ?40 to 85 c si5325b-c-gm 10?808 mhz 36-lead 6 x 6 mm qfn yes ?40 to 85 c si5325c-c-gm 10?346 mhz 36-lead 6 x 6 mm qfn yes ?40 to 85 c
si5325 48 preliminary rev. 0.4 6. package outline: 36-pin qfn figure 4 illustrates the package details for the si5325. table 6 lis ts the values for the di mensions shown in the illustration. figure 4. 36-pin quad flat no-lead (qfn) table 6. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.80 0.85 0.90 l 0.50 0.60 0.70 a1 0.00 0.02 0.05 ? ??12o b 0.18 0.25 0.30 aaa ? ? 0.10 d 6.00 bsc bbb ? ? 0.10 d2 3.95 4.10 4.25 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 6.00 bsc eee ? ? 0.05 e2 3.95 4.10 4.25 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jede c outline mo-220, variation vjjd. 4. recommended card reflow profile is per the je dec/ipc j-std-020 specif ication for small body components.
si5325 preliminary rev. 0.4 49 7. recommended pcb layout figure 5. pcb land pattern diagram table 7. pcb land pattern dimensions dimension min max e 0.50 bsc. e5.42 ref. d5.42 ref. e2 4.00 4.20 d2 4.00 4.20 ge 4.53 ? gd 4.53 ? x?0.28 y0.89 ref. ze ? 6.31 zd ? 6.31 notes (general): 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per th e ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum material conditi on (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes (solder mask design): 1. all metal pads are to be non-solder mask defined (n smd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes (stencil design): 1. a stainless steel, laser-cut and electro-polished stenc il with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pa d size should be 1:1 for the perimeter pads. 4. a 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. notes (card assembly): 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the je dec/ipc j-std-020 specif ication for small body components.
si5325 50 preliminary rev. 0.4 8. top mark mark method: laser font size: 0.80 mm right-justified line 1 marking: si5325q customer part number q = speed code: a, b, c, d see ordering guide for options. line 2 marking: c-gm c = product revision g = temperature range ?40 to 85 c (rohs6) m = qfn package line 3 marking: yywwrf yy = year ww = work week r = die revision f = internal code assigned by the assembly hous e. corresponds to the year and work week of the mold date. line 4 marking: pin 1 identifier circle = 0.75 mm diameter lower-left justified xxxx internal code
si5325 51 preliminary rev. 0.4 d ocument c hange l ist revision 0.23 to revision 0.24 ? clarified that the two outputs have a common, higher frequency source on page 1. ? changed lvttl to lvcmos in table 2, ?absolute maximum ratings,? on page 5. ? added figure 1, ?typical phase noise plot,? on page 4. ? updated ?2. pin descriptions: si5325?. ?? removed references to late ncy control, inc, and dec. ?? changed font for register names to underlined italics. ? updated "5. ordering guide" on page 47. ? added ?7. recommended pcb layout?. revision 0.24 to revision 0.25 ? updated section "2. pin descriptions: si5325" on page 9. revision 0.25 to revision 0.26 ? removed figure 1. ?typ ical phase noise plot.? ? changed pins 11 and 15 from nc to vdd in ?2. pin descriptions: si5325?. revision 0.26 to revision 0.3 ? changed 1.8 v operating range to 5%. ? updated table 1 on page 4. ? updated table 2 on page 5. ? added page 6. ? updated "1. functional description" on page 8. ? clarified "2. pin descriptions: si5325" on page 9 including pull-up/pull-down. revision 0.3 to revision 0.4 ? added register map ? lowered minimum ckout frequency ? updated spec tables ?? esd tolerance, table 2 on page 5 ?? minimum input and output clock frequencies, table 1 on page 4 ?? absolute maximum vdd voltage, table 2 on page 5 ? added to spec table ?? ckin voltage limits, table 2 on page 5 ?? typical jitter and phase noise values, table 1 on page 4 ? no bypass mode with cmos outputs
si5325 52 preliminary rev. 0.4 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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